The present invention relates to a semiconductor integrated circuit device provided as an IP (Intellectual Property), etc., a method of manufacturing the device, and a medium of storing a processing procedure for deciding the number of delay circuits integrated in the semiconductor integrated circuit device used for designing the device, more particularly to a semiconductor integrated circuit device which guarantees the properties for writing in and reading from a memory provided therein, as well as a method of manufacturing the device and a medium used when in designing the device.
In the case of conventional cache memories, data is read from the bit lines driven with a weak current of each memory cell and the weak signal is amplified by a sense amplifier.
Usually, when a potential difference between two bit lines is 100 mV, the sense amplifier is enabled. However, because the time of reading from such a cache memory is less when the sense amplifier is enabled with a potential difference lower than 100 mV, the performance of the cache memory is improved. If the sense amplifier is enabled with an extremely small potential difference, however, the amplification will malfunction; a correct value is not amplified and a wrong value is output if the current in a memory cell is reduced with a process variation or if an offset occurs in the threshold voltage of an input MOS transistor of the sense amplifier. More concretely, it is very important to decide the time for enabling the sense amplifier when in designing.
Conventionally, the timing for enabling the sense amplifier is changed and measured, thereby deciding the optimized timing by processing the metallic line of the sense amplifier with the use of a focused ion beam (FIB) after a trial cache memory is formed on a silicon wafer. If the FIB is used, however, only one timing is set for one chip. In addition, a whole day is required for the processing.
On the other hand, a conventional well-known technique for such a timing decision is disclosed in ICCSS Digest of Technical Papers (pp.236-237) 1998. This document describes that the timing of the object programmable cache memory is changed after the manufacturing.
Although conventional example publicly known is only in theory and unworkable in practice, the present inventor et al has found, as a result of a preliminary examination that a long time is required for testing the memory from external in the on-chip timing adjustment on the basis of the conventional technique and this causes many processes to be needed for finding operation conditions of the object LSI.
More concretely, there has been no well-known means for operating an LSI provided with an on-chip memory using an element whose process condition is uncertain so as not to be controlled (or to be controlled less) from external (ex., an IC tester).
Furthermore, there is no well-known method for adjusting such a timing to a production variation after the chip is manufactured if a CPU, a cache memory, and a DRAM used as a secondary cache are used together.
Under such the circumstances, it is an object of the present invention to compose a semiconductor integrated circuit device provided with such a memory as an SRAM so as to further include a plurality of delay circuits for delaying a sense amplifier enable signal from a clock signal respectively and means for deciding the minimum number of delay circuits for assuring the normal operation of the memory.
Furthermore, it is another object of the present invention to compose a semiconductor integrated circuit device, wherein the means for deciding the minimum number of delay circuits is a CPU which can change the number of delay circuits, write a predetermined value in each cell of the memory, read the written value and compare it with the written value, thereby confirming the normal operation of the memory, then decide the minimum number of delay circuits from among the delay circuit numbers, each of which assures the normal operation of the memory.
Furthermore, it is further another object of the present invention to compose a semiconductor integrated circuit device, wherein the CPU includes a BIST circuit for testing the memory, and the BIST circuit comprises a pattern generator for generating addresses and write data, a pattern comparator for comparing written data with read data, and an output register for outputting the comparison result.
Furthermore, it is further another object of the present invention to compose a semiconductor integrated circuit device, wherein each of the delay circuits comprises an inverter delay circuit and a delay circuit number selector circuit. The delay circuit number selector circuit comprises a register for storing a delay circuit selected number written by the CPU, and a decoder circuit for reading the delay circuit selected number stored in the register, thereby controlling the number of inverter circuits. The delay circuit further includes another circuit for fixing the number of delay circuits by blowing off a fuse after deciding the minimum number of delay circuits.
It is further another object of the present invention to provide a method for manufacturing the above semiconductor integrated circuit device, wherein the CPU selects a change of the number of the delay circuits, confirms the normal operation of each cell of the memory, decides the optimized number of the delay circuits, and fixes the number of the delay circuits by blowing off a fuse, or by other means after the circuits of the semiconductor integrated circuit device are formed.
Because the IP supplier composes a computer readable medium for storing net list data for circuit simulation of the above semiconductor integrated circuit device provided with a memory, as well as a medium for storing a processing procedure for deciding the number of delay circuits integrated in the semiconductor integrated circuit device so as to optimize the timing for delaying the sense amplifier enable signal from a clock signal according to a result of circuit simulation of the semiconductor integrated circuit device and the IP user uses the medium, it is possible to make it easier to design an LSI peculiar to the IP user.